This invention relates to time-to-digital conversion (xe2x80x9cTDCxe2x80x9d), more specifically to time to digital conversion methods and apparatus which use a differential period between frequency-mismatched oscillators to measure time between events to high resolution. The invention has particular application in measuring jitter characteristics in high frequency digital signals. Specific embodiments of the invention are useful for on-board or on-chip self testing of timing circuits such as phase-locked loops (xe2x80x9cPLLsxe2x80x9d), delay-locked loops (xe2x80x9cDLLsxe2x80x9d), and serialiser/deserializers. Another aspect of the invention relates to a finely tunable digital ring oscillator suitable for use in TDC systems according to the invention.
The timing of signals in high speed digital systems can be important to the proper operation of such systems. There is a need for ways to measure time characteristics of digital signals. Jitter is an example of such a time characteristic. Jitter is an important characteristic of high-speed digital signals generally. While there exist sophisticated stand-alone devices capable of measuring jitter in high-speed digital signals, such devices tend to be extremely complicated and expensive. Jitter testing typically requires a long test time. Further, where the signal to be tested is internal to an integrated circuit, it may not be practical to use a stand-alone device to test for jitter.
Timing circuits such as phase-locked loops, delay-locked loops, and serializers/deserializers are used widely in many high-speed integrated circuits. These circuits are used in many applications. Some examples are synthesizing clock signals, recovering data, realigning clock edges and timing the transmission of data.
Jitter in the outputs of such timing circuits can is cause malfunctions. These malfunctions can be very difficult to diagnose. As complex-System on Chip (xe2x80x9cSOCxe2x80x9d) integrated circuits become even more complicated and clock speeds increase into the gigahertz range, it becomes increasingly costly and time consuming to test such circuits.
The definition of jitter varies depending on the field of application. In sequential circuits, e.g. CPUs, jitter is defined as the variation of the clock period, known as xe2x80x9ccycle-to-cyclexe2x80x9d or xe2x80x9cperiod jitterxe2x80x9d. As shown in FIG. 1A, period jitter samples are collected by measuring the duration of each period of the signal IN1.
For both period and accumulative jitter measurements, M jitter samples are collected to calculate jitter characteristics, such as rms, peak-to-peak, or frequency components. For example, the rms jitter may be obtained by performing the following computations:                               T                      J            ⁢                          xe2x80x83                        ⁢                          (              rms              )                                      =                                            1              M                        ⁢                          xe2x80x83                        ⁢                                          ∑                                  i                  =                  0                                                  M                  -                  1                                            ⁢                              xe2x80x83                            ⁢                                                (                                                                                    T                        J                                            ⁢                                              xe2x80x83                                            ⁢                                              (                        i                        )                                                              -                                          T                      _                                                        )                                2                                                                        (        1        )            
where       T    _    =            1      M        ⁢          xe2x80x83        ⁢                  ∑                  i          =          0                          M          -          1                    ⁢              xe2x80x83            ⁢                        T          J                ⁢                  xe2x80x83                ⁢                  (          i          )                    
is the estimate of average signal period.
Some jitter specifications for PLLs used in digital communication interfaces are intrinsic jitter, jitter tolerance and jitter transfer. These specifications are given in standards for each application (e.g., see Bell Research Laboratories SONET transport systems: Common criteria network element architectural features GR-253 core, Issue 1, pp. 5-81, December, 1994 for SONET interfaces).
In serial communication applications, jitter can be defined as the short-term variations of a digital signal""s significant instants, e.g. rising edges, from their ideal position in time. Such jitter is often denoted as xe2x80x9caccumulative jitterxe2x80x9d and is described as a phase modulation of a clock signal. In a clock synthesis circuit, where the absolute jitter is important, often a jitter-free (practically low-jitter) reference signal is used for jitter measurement. In such a case, the difference between the position of corresponding edges of the signal (IN1) relative to the reference clock (REF) indicates the jitter. FIG. 1B illustrates how accumulative jitter samples, TJ(I) for I=1, . . . , N can be collected using a TDC.
Sometimes, the relative jitter between two signals is of interest if neither of the two signals is a jitter-free signal, e.g. in data recovery circuits. FIG. 1C shows how relative jitter between the edges of signal IN1 and IN2 can be measured using a TDC.
Intrinsic jitter is defined as the jitter at the output of the PLL when the input is jitter-free. This is often expressed in terms of unit interval UI, which is defined as the period of a signal with a frequency equal to the average frequency of the original signal. For example in a 155.54 MHz SONET network application, 1 UI is 6.429 ns.
Functional testing is typically used to test today""s high-speed timing circuits. Functional testing, however, does not guarantee correct operation over all operational conditions. Structural test methods are proposed as test solutions, but most of them are too intrusive (i.e. the testing itself has a significant effect on the performance of the circuit) or provide poor correlation to important specifications such as jitter. Jitter specifications are typically the single most important set of specifications for a high-speed timing circuit. Jitter specifications include intrinsic jitter, jitter transfer functions and jitter tolerance. Testing such a circuit to determine whether its actual jitter characteristics meet its specifications is a significant problem.
There is a need for systems capable of measuring jitter characteristics of high-speed digital signals. There is a particular need for such systems capable of measuring jitter in timing circuits internal to complicated integrated circuits.
Various authors have proposed methods for testing devices such as PLLs. All of these proposed methods have disadvantages. R. J. A. Harvey et al. Test evaluation for complex mixed-signal IC""s by introducing layout dependent faults, IEEE Colloquium on Mixed Signal VLSI Test, pp. 6/1-8, 1993 suggests testing PLLs by performing partial specification testing by measuring lock range, lock time and power supply current. Dalmia et al. Power supply current monitoring techniques for testing PLLs Proc. of Asian Test Symposium, pp. 366-371, 1997 and Dalmia et al., U.S. Pat. No. 5,835,501 disclose the use of power supply current monitoring for PLL testing.
Devarayanadurg et al. Hierarchy based statistical fault simulation of mixed signal IC""s Int. Test Conf. pp. 521-527, 1996 and Goteti et al. DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1, Proc. of Custom Integrated Circuits Conf. pp. 210-213, 1997 propose methods for efficient fault simulation of PLLs and suggest lock frequency range measurement for PLL testing.
Although a combination of these techniques may provide an effective test result, it is difficult to correlate the test results to important jitter specifications. This is partly because simulating jitter for fault-free and faulty circuits is extremely difficult due to a lack of tools capable of simulating noise in non-linear dynamic circuits.
Azias et al. A unified digital test technique for PLLs using reconfigurable VCO Proc. of Int. Mixed Signal Test Workshop, 1999 discloses a reconfiguration technique for testing ring oscillator-based PLLS. This technique has the advantage of being compatible with digital test methods, but it requires reconfiguring sensitive parts of a PLL. Also, it exhibits the problem of unknown correlation of test results and functional specifications.
S. Sunter et al. BIST for phase-locked loops in digital applications, Proc. of Int. Test Conf. pp. 532-540, 1999 discloses a BIST circuit capable of measuring lock range and loop gain of a PLL in addition to performing a jitter test. Methods which use this circuit to measure jitter depend on bit error rate (BER) and so can only provide statistical information about jitter. Such methods may give pessimistic estimates of jitter in noisy digital environments. This might lead to discarding some good devices.
U.S. Pat. Nos. 5,663,991 and 5,889,435 disclose on-chip jitter measurement techniques for testing PLL circuits. The BIST circuits proposed in these patents are mixed-signal and their resolution is limited to one gate delay. This is inadequate for testing high-speed PLLs.
Veillette et al. On-chip measurement of the jitter transfer function of charge-pump phase locked loops, Int. Test Conf. pp. 776-785, 1997 disclose a jitter transfer function measurement circuit. This circuit does not have sufficient resolution for intrinsic jitter testing.
Veillette et al., Stimulus generation for built in self test of charge pumped phase locked loops, Int. Test Conf. pp. 698-707, 1998 proposes a method for generating jitter at the input of a PLL for jitter transfer testing. This method, however, requires reconfiguration of the feedback in the PLL loop, which could affect the performance of the loop.
Another on-chip jitter test method is to determine jitter by measuring time intervals between the significant edges of one or two signals. Such measurement can be done with a time-to-digital converter (TDC). A TDC produces a digital output representing the time elapsed between two temporally separated events. FIGS. 1A, 1B and 1C illustrate respectively how period, accumulative jitter, and relative jitter can be measured through the use of a TDC 10.
Various TDC circuits have been used in physics experiments. It has been suggested that such TDC circuits could be used in jitter measurement. Existing TDC circuits occupy large areas, do not provide high resolution, and rely heavily on matching of the elements.
Kelkar et al. U.S. Pat. No. 5,663,991 disclose the use of a controlled delay line in an on-chip jitter measurement method. This circuit suffers from the same limitations as most TDCs.
A classic method of measuring a time interval is to start a counter at the beginning of the interval and stop it when the interval ends. The resulting number in the counter will be proportional to the time interval. The resolution in this method is the period of the clock controlling the counter. To measure intrinsic jitter of a high-speed PLL (e.g. a 155 MHz clock synthesis PLL), where a high resolution in the range of 20 ps is required, a clock frequency of 50 GHZ would be needed. This method is not suitable for on-chip applications where the maximum clock available is in the range of a few hundreds of MHz.
Santos, A CMOS delay locked and sub-nanosecond time-to-digital converter chip, IEEE Trans on Nuclear Science, vol. 43, pp. 1717-1719, June, 1996 discloses a TDC based on the use of a delay chain. In this circuit, the output of the delay elements in the delay chain are set HIGH as the START rising edge travels through them. A delay locked loop (DLL) is used to calibrate the delay elements to a known delay. Such a calibration requires very good matching between all the delay elements in both the delay chain and the DLL.
Arai, A time digitizer CMOS gate array with a 250 ps time resolution, IEEE Journal of Solid-State Circuits, v. 31, pp. 212-220, February, 1996 discloses an alternative TDC in which an analog delay chain and DLL are combined. This obviates the need for element matching. In both of the schemes of Santos and Arai the DLL and the controlled delay elements are analog.
A fully digital TDC could be made by eliminating the DLL and using digital gates as delay elements. The trade-off is decreased accuracy due to the quantization error associated with calibration reference inputs. The resolution Txcex94 of such methods without time interpolation is limited to one gate delay at best. In typical 0.35 xcexcm CMOS technology, the smallest gate delay is approximately 50 ps, whereas a resolution and precision of about 20 ps is required for functional testing of high-speed PLLs with 155 MHz center frequency. Also, since this delay is dependent on process variations and temperature, the resolution in such schemes is not controllable.
Christiansen, An integrated high resolution CMOS timing generator based on an array of delay locked loops, IEEE Journal of Solid-State Circuits, v. 31, pp. 952-957, February, 1996, proposes the use of an array of DLLs to improve the measurement resolution. Mota et al. A high resolution time interpolator based on a delay locked loop and an RC delay line, IEEE Journal of Solid-State Circuits, v. 34, pp. 1360-1366, October, 1999 propose the use of an RC delay line to increase the measurement resolution through time interpolation. Although resolutions in the range of 25 ps (rms) have been reported in these papers, the design of these circuits require a high degree of matching. Also, the design and layout of the DLL need to take into account the presence of significant power supply noise in large mixed-signal ICs.
Kalisz et al., Field programmable gate array based time to digital converter with 200 ps resolution, IEEE Trans. on Instrumentation and Measurement, v. 46, pp. 51-55, February, 1997 propose a Vernier delay technique based on using two delay chains. One chain is composed of gates (each with a delay of xcfx84g). The other chain is made of latches (each with a delay of xcfx84l). In this technique, the time quantization step is the difference between the delay of the delay elements in the two delay chains. A difficulty with this technique is that, since gates and latches are very different structures, xcfx84g and xcfx84l are likely to differ significantly. This makes it difficult to achieve high resolution (in the range of 20 ps or less).
All the schemes mentioned above require good matching of the elements in the delay chains to achieve good accuracy. This is difficult to achieve within an acceptable accuracy under typical process variations. As the time interval to be measured becomes longer, more elements must be added to the delay chains, making it even more difficult to assure matching of delays in the chains. When more elements are added, the elements must be placed further apart and more routing delay will have to be accounted for. Therefore, these schemes make it difficult to provide acceptable TDC linearity. In addition, these schemes do not lend themselves well to automatic place and route. Furthermore, the resolution is set by the process parameters on each chip and cannot be controlled or adjusted.
There is a need for a system capable of measuring directly the jitter characteristics of timing circuits on integrated circuit chips, including timing circuits such as PPLs. Such a system should ideally be:
compact (i.e. small in area compared to the circuit under test (xe2x80x9cCUTxe2x80x9d));
robust (i.e. resistant to process variations, temperature and power supply variations);
provide a digital output (i.e. the system should generate one or more digital signatures which can be sent off-chip at relatively low speed, e.g. serially);
accurate (measurement accuracy must be sufficient for the test);
capable of being calibrated (i.e. the system should be calibration-free, self-calibrating, or use readily available signals to the chip for calibration); and,
have little or no impact on the performance of the CUT.
One aspect of this invention provides a time to digital converter (TDC). The TDC comprises a timing circuit which includes first and second digital oscillators. The oscillators produce first and second clock signals respectively. The first and second oscillators have different periods. The invention uses the accurately known average difference between the periods of the first and second oscillators to make high resolution time measurements. At least one of the oscillators has a variable period. In preferred embodiments of the invention, at least one of the oscillators comprises a plurality of digitally controllable delay elements. The delay elements, when activated alter the period of oscillation of the oscillator.
The TDC also includes a coincidence detector connected to generate a coincidence signal when a reference point in the first clock signal has a known time relationship to a corresponding reference point on the second clock signal. In preferred embodiments of the invention, the coincidence detector comprises a flip flop or other memory device which is set when an edge of the first clock signal coincides with a corresponding edge of is the second clock signal.
A first counter is connected to count a number of cycles of the first oscillator until the coincidence detector generates the coincidence signal. The number is related to the duration of an interval between starting the first oscillator and starting the second oscillator.
A resolution adjustment circuit is connected to start the first and second oscillators at times separated by a known interval, compare the number to a threshold and, if the number is not at least equal to a threshold value, alter the period of at least one of the oscillators by activating or deactivating one or more of the digitally controllable delay elements.
In a preferred, dual resolution, embodiment, the first and second oscillators are switchable between a first state wherein a difference in periods of the first and second signals is Txcex941 and a second state wherein a difference in periods of the first and second signals is Txcex942 where Txcex942 less than Txcex941; and the time to digital converter comprises a resolution switching control circuit connected to switch the timing circuit among its states, a second counter connected to count a number of edges of the first signal between a START signal and a time when the timing circuit is switched away from its first state, the first counter connected to count a number of edges of the first signal between the time when the timing circuit is switched into its second state and the time when coincidence signal is generated.
Another aspect of the invention provides a time to digital converter comprising a timing circuit comprising first and second digital oscillators producing first and second clock signals respectively. The first and second oscillators are switchable between a plurality of states including a first state wherein a difference in periods of the first and second signals is Txcex941 and a second state wherein a difference in periods of the first and second signals is Txcex942 where Txcex942 less than Txcex941. A resolution switching control circuit is connected to switch the timing circuit between its states when the reference point of the first clock signal approaches a predetermined time relationship with the reference point of the second clock signal. A coincidence detector connected to generate a coincidence signal when a reference point in the first clock signal has a known time relationship to a corresponding reference point on the second clock signal. A first counter is connected to count a number of edges of the first clock signal between the time when the timing circuit is switched from its first state to its second state and the time when the coincidence signal is generated and a second counter is connected to count a number of edges of the first signal between a START signal and a time when the timing circuit is switched from its first state to its second state.
In a preferred embodiment of the invention, the resolution switching control circuit comprises a delay element connected to provide a delayed first clock signal and a coincidence detector connected to generate a coincidence signal when a reference point in the second clock signal has a known time relationship to a corresponding reference point on the delayed first clock signal. Most preferably the delay element has a first state resulting in a first delay of the delayed first clock signal and a second state resulting in a second delay of the delayed first clock signal different from the first delay.
A further embodiment of the invention provides a digital timing circuit for generating first and second digital output signals having first and second periods. The timing circuit comprises a first ring oscillator triggered by a first control signal and generating a first clock signal; and a second ring oscillator triggered by a second control signal and generating a second control signal. At least one of the oscillators comprises a plurality of digitally controllable delay elements. The delay elements, when activated alter the period of the oscillator. The timing circuit comprises a coincidence detector connected to generate a coincidence signal when a reference point in the first clock signal has a known time relationship to a corresponding reference point on the second clock signal. A counter is connected to count a number, N, of cycles of the first oscillator between the first control signal and the coincidence signal. A resolution adjustment circuit connected to generate the first and second control signals at times separated by a known interval, compare the number N to a threshold and, if N is not at least equal to a threshold value altering the period of at least one of the oscillators by activating or deactivating one or more of the digitally controllable delay elements.
A still further aspect of the invention provides a method for producing first and second digital signals having first and second periods. The method comprises providing a pair of digital oscillators; starting the first oscillator and starting the second oscillator a time period Td after starting the first oscillator; counting a number N of cycles of the first oscillator until a reference point on the first signal coincides with a corresponding reference point on the second signal; if N is not at least equal to a threshold value altering the period of at least one of the oscillators and repeating these steps until N is at least equal to the threshold value.
In preferred embodiments of the invention, varying a period of at least one of the oscillators comprises changing a state of a controllable delay element.
A yet further aspect of the invention provides a method for time to digital conversion comprising providing first and second digital oscillators having periods which differ wherein the first and second oscillators are switchable between a first state wherein a difference in periods of the first and second signals is Txcex941 and a second state wherein a difference in periods of the first and second signals is Txcex942 where Txcex942 less than Txcex941; starting the first oscillator upon the occurrence of a first control signal and starting the second oscillator on the occurrence of a second control signal a time Td later; when the reference points occur within a known time delay of one another switching the oscillators to their second state; counting a number NC of edges of the first clock signal which occur between the first control signal and a time when the oscillators are switched to their second state; and, counting a number NF of edges of the first clock signal which occur between the time when the oscillators are switched to their second state and a time when the reference points have a known time relationship.
The method may include estimating the difference between the first and second oscillator periods (Txcex942 and Txcex941) by acquiring a first set of the numbers NF and NC for Td having a known value Tref while the known time delay has a first value and a second set of the numbers NF and NC for Td having a known value Tref, or a known multiple of Tref, while the known time delay has a second value, averaging NF and NC for each set of measurements and computing the resolutions Txcex942 and Txcex941 from the average values of NF and NC for the two sets of measurements.
Another aspect of the invention provides a frequency tunable digital ring oscillator comprising a closed signal path defined at least in part by a plurality of series connected delay elements each having an input and an output the delay elements comprising at least one digitally controllable delay element. The digitally controllable delay element comprises a gate connected in series with the signal path and a tri-state device having an input connected to an output of the gate and a control connection connected to a control device.
The tri-state device may be a tri-NOT gate or a tri-state buffer, for example.
Further features of various embodiments of specific embodiments of the invention.